Developing TEI-Aware Ultralow-Power SoC Platforms for IoT End Nodes

Ranging from circuit-level characterization to designing a platform architecture, developing design automation tool, and fabricating System on Chip (SoC), this article deals with the entire development process for ultralow-power (ULP) SoCs Internet-of-Things (IoT) end nodes. More precisely, first focuses unique characteristics of ULP circuits, temperature effect inversion (TEI), i.e., delay circuits decreases increasing temperature. Existing TEI-aware low-power (TEI-LP) techniques have incredible potential further reduce power consumption conventional SoCs, but there is critical limitation be widely adopted in real SoCs. To address realize that can fully benefit TEI-LP techniques, proposes new TEI-inspired SoC (TIP) architecture. On top that, taking into account highly complex, time consuming, labor-intensive these may hinder their widespread use IoT nodes, presents electronic tool accelerate development, RISC-V express (RVX). Finally, by using RVX, introduces TIP prototyping chip fabricated 28-nm FD-SOI technology. This demonstrates savings up 35% achieved lowering supply voltage 0.54 0.48 V at 25 °C 0.44 80 while continuing operate target 50-MHz clock frequency.